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19-1002; Rev 0; 8/04
KIT ATION EVALU ABLE AVAIL
12-Bit, 80Msps, 3.3V ADC
General Description Features
Excellent Dynamic Performance 68.2dB/68.0dB SNR at fIN = 3MHz/70MHz 89.3dBc/85.1dBc SFDR at fIN = 3MHz/70MHz 3.3V Low-Power Operation 373mW (Single-Ended Clock Mode) 399mW (Differential Clock Mode) 3W (Power-Down Mode) Differential or Single-Ended Clock Fully Differential or Single-Ended Analog Input Adjustable Full-Scale Analog Input Range: 0.35V to 1.15V Common-Mode Reference CMOS-Compatible Outputs in Two's Complement or Gray Code Data-Valid Indicator Simplifies Digital Design Data Out-of-Range Indicator Miniature, 40-Pin Thin QFN Package with Exposed Paddle Evaluation Kit Available (Order MAX1211EVKIT)
MAX1208
The MAX1208 is a 3.3V, 12-bit, 80Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts singleended or differential signals. The MAX1208 is optimized for low power, small size, and high dynamic performance in baseband applications. Powered from a single 3.0V to 3.6V supply, the MAX1208 consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.2dB at an input frequency of 32.5MHz. In addition to low operating power, the MAX1208 features a 3W power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1208 to use the internal 2.048V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from 0.35V to 1.15V. The MAX1208 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX1208 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE). ADC conversion results are available through a 12-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide 1.7V to 3.6V supply, allowing the MAX1208 to interface with various logic levels. The MAX1208 is available in a 6mm x 6mm x 0.8mm, 40-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40C to +85C) temperature range. See the Pin-Compatible Versions table for a complete family of 14-bit and 12-bit high-speed ADCs.
Ordering Information
PART TEMP RANGE PINPACKAGE 40 Thin QFN (6mm x 6mm x 0.8mm) PKG CODE T4066-3
MAX1208ETL
-40C to +85C
Pin-Compatible Versions
PART MAX12553 MAX1209 MAX1211 MAX1208 MAX1207 MAX1206 SAMPLING RATE (Msps) 65 80 65 80 65 40 RESOLUTION (BITS) 14 12 12 12 12 12 TARGET APPLICATION IF/Baseband IF IF Baseband Baseband Baseband
Applications
Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation Low-Power Data Acquisition
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12-Bit, 80Msps, 3.3V ADC MAX1208
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D11 Through D0 I.C., DAV, DOR to GND ...-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/C above +70C)........................2105.3mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INP, INN) Differential Input Voltage Range Common-Mode Input Voltage Input Capacitance (Figure 3) CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency Figure 6 8.5 fCLK 80 5 MHz MHz Clock cycles dBFS dB CPAR CSAMPLE Fixed capacitance to ground Switched capacitance VDIFF Differential or single-ended inputs 1.024 VDD / 2 2 1.9 V V pF INL DNL fIN = 20MHz fIN = 20MHz, no missing codes over temperature VREFIN = 2.048V VREFIN = 2.048V -0.83 12 0.65 0.35 0.25 1.0 0.92 5.6 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (differential inputs, Note 2) Small-Signal Noise Floor Signal-to-Noise Ratio SSNF SNR Input at less than -35dBFS fIN = 3MHz at -0.5dBFS fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Signal-to-Noise and Distortion SINAD fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS 65.2 65.4 -68.8 68.2 68.2 68.0 68.1 68.1 67.8 dB
2
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12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Spurious-Free Dynamic Range SYMBOL SFDR CONDITIONS fIN = 3MHz at -0.5dBFS fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Total Harmonic Distortion THD fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Second Harmonic HD2 fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Third Harmonic HD3 fIN = 32.5MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS Intermodulation Distortion Third-Order Intermodulation Two-Tone Spurious-Free Dynamic Range Aperture Delay Aperture Jitter Output Noise Overdrive Recovery Time IMD IM3 SFDRTT tAD tAJ nOUT fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS Figure 4 Figure 4 INP = INN = COM 10% beyond full scale 78.7 MIN TYP 89.3 88.2 85.1 -87.1 -85.0 -81.2 -93 -89 -86.5 -96.8 -95.1 -85.1 -81.1 -84.4 85.4 0.9 <0.2 0.52 1 dBc dBc dBc ns psRMS LSBRM Clock cycles 2.079 V V V mV/mA ppm/C mA dBc dBc -77.2 dBc dBc MAX UNITS
MAX1208
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage COM Output Voltage Differential Reference Output REFOUT Load Regulation REFOUT Temperature Coefficient REFOUT Short-Circuit Current TCREF Short to VDD--sinking Short to GND--sourcing VREFOUT VCOM VREF VDD / 2 VREF = VREFP - VREFN 1.978 2.048 1.65 1.024 35 +50 0.24 2.1
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage REFP Output Voltage VREFIN VREFP (VDD/2) + (VREFIN / 4) 2.048 2.162 V V
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3
12-Bit, 80Msps, 3.3V ADC MAX1208
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER REFN Output Voltage COM Output Voltage Differential Reference Output Voltage Differential Reference Temperature Coefficient REFIN Input Resistance COM Input Voltage REFP Input Voltage REFN Input Voltage Differential Reference Input Voltage REFP Sink Current REFN Source Current COM Sink Current REFP, REFN Capacitance COM Capacitance CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold Differential Input Voltage Swing Differential Input Common-Mode Voltage Input Resistance Input Capacitance DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold VIH 0.8 x OVDD V RCLK CCLK VIH VIL CLKTYP = GND, CLKN = GND CLKTYP = GND, CLKN = GND CLKTYP = high CLKTYP = high Figure 5 1.4 VDD / 2 5 2 0.8 x VDD 0.2 x VDD V V VP-P V k pF VREF IREFP IREFN ICOM VCOM VDD / 2 VREFP - VCOM VREFN - VCOM VREF = VREFP - VREFN VREFP = 2.162V VREFN = 1.138V SYMBOL VREFN VCOM VREF VDD / 2 VREF = VREFP - VREFN CONDITIONS (VDD / 2) - (VREFIN / 4) 1.60 0.969 MIN TYP 1.138 1.65 1.024 25 >50 1.65 0.512 -0.512 1.024 1.1 1.1 0.3 13 6 1.70 1.069 MAX UNITS V V V ppm/C M V V V V mA mA mA pF pF
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)
4
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12-Bit, 80Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Low Threshold Input Leakage Current Input Capacitance CDIN D11-D0, DOR, ISINK = 200A DAV, ISINK = 600A D11-D0, DOR, ISOURCE = 200A Output Voltage High VOH DAV, ISOURCE = 600A Tri-State Leakage Current D11-D0, DOR Tri-State Output Capacitance DAV Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode, fIN = 32.5MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Supply Current IVDD Normal operating mode, fIN = 32.5MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode clock idle, PD = OVDD Normal operating mode, fIN = 32.5MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Power Dissipation PDISS Normal operating mode, fIN = 32.5MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode clock idle, PD = OVDD 3.0 1.7 3.3 2.0 3.6 VDD + 0.3V V V ILEAK COUT CDAV (Note 3) (Note 3) (Note 3) 3 6 OVDD 0.2 V OVDD 0.2 5 A pF pF SYMBOL VIL VIH = OVDD VIL = 0 5 0.2 0.2 CONDITIONS MIN TYP MAX 0.2 x OVDD 5 5 UNITS V A pF
MAX1208
DIGITAL OUTPUTS (D11-D0, DAV, DOR) Output Voltage Low VOL V
113 mA 121 0.001 373 mW 399 0.003 436.3 132.2
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5
12-Bit, 80Msps, 3.3V ADC MAX1208
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS Normal operating mode, fIN = 32.5MHz at -0.5dBFS, OVDD = 2.0V, CL 5pF Power-down mode clock idle, PD = OVDD TIMING CHARACTERISTICS (Figure 6) Clock Pulse Width High Clock Pulse Width Low Data-Valid Delay Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake-Up Time from Power-Down tCH tCL tDAV tSETUP tHOLD tWAKE CL = 5pF (Note 5) CL = 5pF (Note 4, Note 5) CL = 5pF (Note 4, Note 5) VREFIN = 2.048V 7.7 4.2 10 6.25 6.25 6.4 ns ns ns ns ns ms MIN TYP 9.9 0.9 MAX UNITS mA A
Digital Output Supply Current
IOVDD
Note 1: Note 2: Note 3: Note 4: Note 5:
Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. See definitions in the Parameter Definitions section. During power-down, D11-D0, DOR, and DAV are high impedance. Guaranteed by design and characterization. Digital outputs settle to VIH or VIL.
6
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12-Bit, 80Msps, 3.3V ADC MAX1208
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
MAX1208 toc01
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
MAX1208 toc02
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 HD2 HD3 HD4 fCLK = 80.00353MHz fIN = 69.99331395MHz AIN = -0.510dBFS SNR = 68.011dB SINAD = 67.819dB THD = -81.470dBc SFDR = 85.617dBc
MAX1208 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 4 8 HD2 HD3
AMPLITUDE (dBFS)
fCLK = 80.00353MHz fIN = 2.99817879MHz AIN = -0.527dBFS SNR = 68.100dB SINAD = 68.061dB THD = -88.539dBc SFDR = 90.612dBc
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
fCLK = 80.00353MHz fIN = 32.49166395MHz AIN = -0.495dBFS SNR = 68.236dB SINAD = 68.173dB THD = -86.624dBc SFDR = 89.446dBc
0
HD2
HD3
12 16 20 24 28 32 36 40 FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40 FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40 FREQUENCY (MHz)
SINGLE-TONE FFT PLOT (16,384-POINT DATA RECORD)
MAX1208 toc04
SINGLE-TONE FFT PLOT (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 fIN1 + 2 x fIN2 fIN1 + fIN2 2 x fIN1 + fIN2 fIN1 fIN2 fCLK = 80MHz fIN1 = 68.50098MHz AIN1 = -7.043dBFS fIN2 = 71.499MHz AIN2 = -7.041dBFS IMD = -80.988dBc IM3 = -84.424dBc
MAX1208 toc05 MAX1208 toc07
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0
fCLK = 80MHz fIN1 = 43.90137MHz AIN1 = -7.010dBFS fIN2 = 45.90332MHz AIN2 = -7.041dBFS SFDRTT = 87.239dBc IMD = -85.288dBc IM3 = -87.415dBc
0
fIN1 fIN2
2 x fIN1 + fIN2
4
8
12 16 20 24 28 32 36 40 FREQUENCY (MHz)
0
4
8
12 16 20 24 28 32 36 40 FREQUENCY (MHz)
INTEGRAL NONLINEARITY
0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
MAX1208 toc06
DIFFERENTIAL NONLINEARITY
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
1.0
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12-Bit, 80Msps, 3.3V ADC MAX1208
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. SAMPLING RATE
MAX1208 toc08
SFDR, -THD vs. SAMPLING RATE
MAX1208 toc09
POWER DISSIPATION vs. SAMPLING RATE
DIFFERENTIAL CLOCK fIN 32.5MHz CL 5pF
MAX1208 toc10
70 69 68
100 95 90 SFDR, -THD (dBc) 85 80 75 70
fIN 32.5MHz
fIN 32.5MHz
500 450 POWEER DISSIPATION (mW) 400 350 300 250 200
SNR, SINAD (dB)
67 66 65 64 63 62 0 20 40 60 80 100 fCLK (MHz) SNR SINAD
65 60 0 20 40 60 80
SFDR -THD 100
ANALOG + DIGITAL POWER ANALOG POWER 0 20 40 60 80 100
fCLK (MHz)
fCLK (MHz)
SNR, SINAD vs. SAMPLING RATE
MAX1208 toc11
SFDR, -THD vs. SAMPLING RATE
fIN 70MHz
MAX1208 toc12
POWER DISSIPATION vs. SAMPLING RATE
DIFFERENTIAL CLOCK fIN 70MHz CL 5pF
MAX1208 toc13
70 69 68 SNR, SINAD (dB) 67 66 65 64 63 62 0
fIN 70MHz
100 95 90 SFDR, -THD (dBc) 85 80 75 70
450
POWEER DISSIPATION (mW)
400
350
300
250 SFDR -THD 200 0 20 40 60 80 100 0 20 40 60 fCLK (MHz) 80 100 120 fCLK (MHz) ANALOG + DIGITAL POWER ANALOG POWER
SNR SINAD 20 40 60 80 100
65 60
fCLK (MHz)
SNR, SINAD vs. ANALOG INPUT FREQUENCY
MAX1208 toc14
SFDR, -THD vs. ANALOG INPUT FREQUENCY
MAX1208 toc15
POWER DISSIPATION vs. ANALOG INPUT FREQUENCY
DIFFERENTIAL CLOCK fCLK 80MHz CL = 5pF 450
MAX1208 toc16
70 69 68 SNR, SINAD (dB) 67 66 65 64 63 62 61 60 0 25 50 75
fCLK 80MHz
95
fCLK 80MHz
500
85
POWER DISSIPATION (mW) SFDR -THD
90 SFDR, -THD (dBc)
400
80
SNR SINAD 100 125
75
350 ANALOG + DIGITAL POWER ANALOG POWER 300
70 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
8
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12-Bit, 80Msps, 3.3V ADC MAX1208
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
MAX1208 toc17
SFDR, -THD vs. ANALOG INPUT AMPLITUDE
MAX1208 toc18
POWER DISSIPATION vs. ANALOG INPUT AMPLITUDE
DIFFERENTIAL CLOCK fCLK = 80.003702MHz fIN = 32.125257MHz CL 5pF
MAX1208 toc19
75 70 65 SNR, SINAD (dB) 60 55 50 45 40 35 30 25
fCLK = 80.003702MHz fIN = 32.125257MHz
90 85 80 SFDR, -THD (dBc) 75 70 65 60 55 50
fCLK = 80.003702MHz fIN = 32.125257MHz
500
POWER DISSIPATION (mW) SFDR -THD
450
400
350 ANALOG + DIGITAL POWER ANALOG POWER 300
SNR SINAD -40 -35 -30 -25 -20 -15 -10 -5 0
45 40 -40 -35 -30 -25 -20 -15 -10
-5
0
-40
-35
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD vs. ANALOG POWER-INPUT VOLTAGE
MAX1208 toc20
SFDR, -THD vs. ANALOG POWER-INPUT VOLTAGE
MAX1208 toc21
POWER DISSIPATION vs. ANALOG POWER-INPUT VOLTAGE
DIFFERENTIAL CLOCK fCLK = 80.03584MHz fIN = 32.11399MHz CL 5pF
MAX1208 toc22
70 69 68 SNR, SINAD (dB) 67 66 65 64 63 62 61 60 2.6 2.8 3.0 3.2 3.4 SNR SINAD fCLK = 80.03584MHz fIN = 32.11399MHz
100 95 90 SFDR, -THD (dBc) 85 80 75 70 65 60 SFDR -THD 2.6 2.8 3.0 3.2 3.4 fCLK = 80.03584MHz fIN = 32.11399MHz
550 500 POWER DISSIPATION (mW) 450 400 350 300 250 200 ANALOG + DIGITAL POWER ANALOG POWER 2.6 2.8 3.0 3.2 3.4
3.6
3.6
3.6
VDD (V)
VDD (V)
VDD (V)
SNR, SINAD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
MAX1208 toc23
SFDR, -THD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
MAX1208 toc24
POWER DISSIPATION vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE
500 450 SFDR, -THD (dBc) 400 350 300 250 DIFFERENTIAL CLOCK fCLK = 80.03584MHz fIN = 32.11399MHz CL 5pF
MAX1208 toc25
70 69 68 SNR, SINAD (dB) 67 66 65 64 63 62 61 60 1.4
100 95 90 SFDR, -THD (dBc) 85 80 75 70
fCLK = 80.03584MHz fIN = 32.11399MHz
fCLK = 80.03584MHz fIN = 32.11399MHz
550
SNR SINAD 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8
65 60 1.4
SFDR -THD 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8
225 200 1.4
ANALOG + DIGITAL POWER ANALOG POWER 1.8 2.2 2.6 OVDD (V) 3.0 3.4 3.8
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9
12-Bit, 80Msps, 3.3V ADC MAX1208
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. TEMPERATURE
MAX1208 toc26
SFDR, -THD vs. TEMPERATURE
MAX1208 toc27
ANALOG POWER DISSIPATION vs. TEMPERATURE
DIFFERENTIAL CLOCK fCLK = 80.003072MHz fIN = 32.481716MHz
MAX1208 toc28
70 69 68 SNR, SINAD (dB) 67 66 65 64 63 62 61 60 -40 -15 10 35 60 SNR SINAD fCLK = 80.003072MHz fIN = 32.481716MHz
95 93 91 SFDR, -THD (dBc) 89 87 85 83 81 79 77 75 SFDR -THD -40 -15 10 35 60 fCLK = 80.003072MHz fIN = 32.481716MHz
550 ANALOG POWER DISSIPATION (mW) 500 450 400 350 300 250 200
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX1208 toc29
GAIN ERROR vs. TEMPERATURE
VREFIN = 2.048V 2 GAIN ERROR (%FS) 1 0 -1 -2 -3
MAX1208 toc30
0.5 0.4 0.3 OFFSET ERROR (%FS) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -15 10 35 60 VREFIN = 2.048V
3
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
10
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12-Bit, 80Msps, 3.3V ADC MAX1208
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE LOAD REGULATION
MAX1208 toc31
REFERENCE OUTPUT VOLTAGE SHORT-CIRCUIT PERFORMANCE
MAX1208 toc32
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
MAX1208 toc33
2.05 2.04 2.03 2.02 VREFOUT (V) +85C
3.5 3.0 2.5 VREFOUT (V) 2.0 1.5 +25C 1.0 +85C
2.039
2.037 VREFOUT (V)
2.01 2.00 1.99 1.98 1.97 1.96 1.95 -2.0
2.035
2.033
-40C +25C
2.031 0.5 0 -40C 2.029 -3.0 -2.0 -1.0 0 1.0 -40 -15 10 35 60 85 IREFOUT SINK CURRENT (mA) TEMPERATURE (C)
-1.5
-1.0
-0.5
0
0.5
IREFOUT SINK CURRENT (mA)
REFP, COM, REFN LOAD REGULATION
VREFP
MAX1208 toc34
REFP, COM, REFN SHORT-CIRCUIT PERFORMANCE
MAX1208 toc35
3.0 2.5 2.0 1.5 1.0 VREFN 0.5 0 -2 -1 0 SINK CURRENT (mA) 1 2 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE VCOM
3.5 3.0 2.5 VCOM VREFP
VOLTAGE (V)
VOLTAGE (V)
2.0 1.5 1.0 0.5 0 -8 -4 0 SINK CURRENT (mA) 4 8 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE VREFN
______________________________________________________________________________________
11
12-Bit, 80Msps, 3.3V ADC MAX1208
Pin Description
PIN NAME FUNCTION Positive Reference I/O. The full-scale analog input range is (VREFP - VREFN). Bypass REFP to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Place the 1F REFP to REFN capacitor as close to the device as possible on the same side of the printed circuit (PC) board. Negative Reference I/O. The full-scale analog input range is (VREFP - VREFN). Bypass REFN to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Place the 1F REFP to REFN capacitor as close to the device as possible on the same side of the PC board. Common-Mode Voltage I/O. Bypass COM to GND with a 2.2F capacitor. Place the 2.2F COM to GND capacitor as close to the device as possible. This 2.2F capacitor can be placed on the opposite side of the PC board and connected to the MAX1208 through a via. Ground. Connect all ground pins and EP together. Positive Analog Input Negative Analog Input Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer. Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OVDD or VDD to define the differential clock input. Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel capacitor combination of 2.2F and 0.1F. Connect all VDD pins to the same potential. Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of 2.2F and 0.1F. Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6). CMOS Digital Output, Bit 11 (MSB) CMOS Digital Output, Bit 10 CMOS Digital Output, Bit 9 CMOS Digital Output, Bit 8 CMOS Digital Output, Bit 7 CMOS Digital Output, Bit 6 CMOS Digital Output, Bit 5 CMOS Digital Output, Bit 4 CMOS Digital Output, Bit 3
1
REFP
2
REFN
3 4, 7, 16, 35 5 6 8
COM
GND INP INN DCE
9
CLKN
10
CLKP
11 12-15, 36 17, 34
CLKTYP VDD OVDD
18 19 20 21 22 23 24 25 26 27
DOR D11 D10 D9 D8 D7 D6 D5 D4 D3
12
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12-Bit, 80Msps, 3.3V ADC MAX1208
Pin Description (continued)
PIN 28 29 30 31, 32 33 37 38 NAME D2 D1 D0 I.C. DAV PD REFOUT CMOS Digital Output, Bit 2 CMOS Digital Output, Bit 1 CMOS Digital Output, Bit 0 ( LSB) Internally Connected. Leave I.C. unconnected. Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the MAX1208 output data into an external back-end digital circuit. Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a 0.1F capacitor. Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a 0.1F capacitor. In these modes, VREFP - VREFN = VREFIN / 2. For unbuffered external reference-mode operation, connect REFIN to GND. Output Format Select Input. Connect G/T to GND for the two's complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. Exposed Paddle. The MAX1208 relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane. FUNCTION
39
REFIN
40
G/T
--
EP
MAX1208
T/H
+
-
FLASH ADC
DAC
INP T/H INN DIGITAL ERROR CORRECTION D11-D0 OUTPUT DRIVERS STAGE 1 STAGE 2 STAGE 9
STAGE 10 END OF PIPE
D11-D0
Figure 1. Pipeline Architecture--Stage Blocks
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13
12-Bit, 80Msps, 3.3V ADC MAX1208
CLKP CLKN DCE CLKTYP
CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER
MAX1208
VDD GND
BOND WIRE INDUCTANCE 1.5nH INP
VDD
MAX1208
OVDD 12-BIT PIPELINE ADC D11-D0 DAV DOR
CPAR 2pF
*CSAMPLE 1.9pF
INP INN
T/H
DEC
OUTPUT DRIVERS
REFOUT REFIN REFP COM REFN REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS
G/T
BOND WIRE INDUCTANCE 1.5nH INN
VDD
PD
CPAR 2pF
*CSAMPLE 1.9pF
Figure 2. Simplified Functional Diagram
SAMPLING CLOCK
Detailed Description
The MAX1208 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1208 functional diagram.
*THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RSAMPLE =
1 fCLK x CSAMPLE
Figure 3. Simplified Input Track-and-Hold Circuit
capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX1208 supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (VDD / 2). The MAX1208 provides the optimum common-mode voltage of V DD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 10, 11, and 12.
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies up to 70MHz and supports a common-mode input voltage of VDD / 2 0.5V. The MAX1208 sampling clock controls the ADC's switched-capacitor T/H architecture (Figure 3), allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX1208. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires 10ms to power up and settle when power is applied to the MAX1208 or when PD transitions from high to low. REFOUT has approximately 17k to GND when the MAX1208 is in power-down. The internal bandgap reference and its buffer generate VREFOUT to be 2.048V. The reference temperature coefficient is typically +50ppm/C. Connect an external 0.1F bypass capacitor from REFOUT to GND for stability.
14
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
CLKP CLKN tAD ANALOG INPUT tAJ SAMPLED DATA
T/H
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
TRACK
HOLD
Figure 4. T/H Aperture Timing
REFOUT sources up to 1.0mA and sinks up to 0.1mA for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD.
divider, use resistances 10k to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX1208 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.3V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. To operate the MAX1208 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive VCOM to VDD / 2 5%, and drive REFP and REFN such that V COM = (VREFP + VREFN / 2. The full-scale analog input range is (VREFP - VREFN).
Analog Inputs and Reference Configurations
The MAX1208 full-scale analog input range is adjustable from 0.35V to 1.15V with a commonmode input range of VDD / 2 0.5V. The MAX1208 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). To operate the MAX1208 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, VREFN = VDD / 2 - VREFIN / 4. The REFIN input impedance is very large (>50M). When driving REFIN through a resistive
Table 1. Reference Modes
VREFIN REFERENCE MODE Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN / 4 VREFN = VDD / 2 - VREFIN / 4 Buffered External Reference Mode. Apply an external 0.7V to 2.3V reference voltage to REFIN. The full-scale analog input range is VREFIN / 2: VCOM = VDD / 2 VREFP = VDD / 2 + VREFIN / 4 VREFN = VDD / 2 - VREFIN / 4 Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is (VREFP - VREFN).
35% VREFOUT to 100% VREFOUT
0.7V to 2.3V
<0.4V
______________________________________________________________________________________
15
12-Bit, 80Msps, 3.3V ADC
All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2F capacitor to GND. Bypass REFP and REFN each with a 0.1F capacitor to GND. Bypass REFP to REFN with a 1F capacitor in parallel with a 10F capacitor. Place the 1F capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a 0.1F capacitor. For detailed circuit suggestions, see Figures 13 and 14.
MAX1208
VDD S1H
MAX1208
10k
CLKP 10k S2H S1L 10k CLKN 10k SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. DUTY-CYCLE EQUALIZER
Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP)
The MAX1208 accepts both differential and singleended clock inputs. For single-ended clock-input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock-input operation, connect CLKTYP to OVDD or VDD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the MAX1208 is powered down (Figure 5). Low clock jitter is required for the specified SNR performance of the MAX1208. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.2dB of SNR with an input frequency of 32.5MHz, the system must have less than 1.9ps of clock jitter.
S2L GND
Figure 5. Simplified Clock Input Circuit
The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the MAX1208 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. Disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5mA.
System Timing Requirements
Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN).
Clock Duty-Cycle Equalizer (DCE)
Enable the MAX1208 clock duty-cycle equalizer by connecting DCE to OVDD or VDD. Disable the MAX1208 clock duty-cycle equalizer by connecting DCE to GND.
16
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
DIFFERENTIAL ANALOG INPUT (INP-INN) (VREFP - VREFN) N+3 N-3 N-2 N-1 N N+1 N+2 N+4 N+5 N+6 N+7 N+8 tAD CLKN CLKP tDAV DAV tSETUP D11-D0 tHOLD N-3 8.5 CLOCK-CYCLE DATA LATENCY DOR N-2 N-1 N N+1 N+2 N+3 N+4 N+5 tSETUP N+6 N+7 N+8 N+9 tHOLD tCL tCH N+9
(VREFN - VREFP)
Figure 6. System Timing Diagram
Data-Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6). The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns. With the duty-cycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D11-D0 and DOR are valid from 7.7ns before the rising edge of DAV to 4.2ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.4ns (tDAV) delay from the falling edge of CLKP. DAV is high impedance when the MAX1208 is in power-down (PD = high). DAV is capable of sinking and sourcing 600A and has three times the drive strength of D11-D0 and DOR. DAV is typically used to latch the MAX1208 output data into an external backend digital circuit. Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX1208 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX1211 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) to (VREFN - VREFP). Signals out-
side this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6. DOR is synchronized with DAV and transitions along with the output data D11-D0. There is an 8.5 clockcycle latency in the DOR function as with the output data (Figure 6). DOR is high impedance when the MAX1208 is in power-down (PD = high). DOR enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD's falling edge. Digital Output Data (D11-D0), Output Format (G/T) The MAX1208 provides a 12-bit, parallel, tri-state output bus. D11-D0 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX1208 output data format is either Gray code or two's complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two's complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code-conversion example. The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input:
VINP - VINN = (VREFP - VREFN ) x 2 x CODE10 - 2048 4096
for Gray code (G/T = 1)
______________________________________________________________________________________
17
12-Bit, 80Msps, 3.3V ADC
Keep the capacitive load on the MAX1208 digital outputs D11-D0 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1208 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the MAX1208 from heavy capacitive loading. To improve the dynamic performance of the MAX1208, add 220 resistors in series with the digital outputs close to the MAX1208. Refer to the MAX1211 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220 series resistors.
MAX1208
VINP - VINN = (VREFP - VREFN ) x 2 x
CODE10 4096
for two's complement (G/T = 0) where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. Digital outputs D11-D0 are high impedance when the MAX1208 is in power-down (PD = high). D11-D0 transition high 10ns after the rising edge of PD and become active 10ns after PD's falling edge.
Power-Down Input (PD)
The MAX1208 has two power modes that are controlled with the power-down digital input (PD). With PD low, the
Table 2. Output Codes vs. Input Voltage
GRAY CODE OUTPUT CODE (G/T = 1) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11D0 D11D0 (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x800 0x800 0x801 0xC03 0xC01 0xC00 0x400 0x401 0x001 0x000 0x000 +4095 +4095 +4094 +2050 +2049 +2048 +2047 +2046 +1 0 0 TWO'S-COMPLEMENT OUTPUT CODE (G/T = 0) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11D0 D11D0 (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x7FF 0x7FF 0x7FE 0x002 0x001 0x000 0xFFF 0xFFE 0x801 0x800 0x800 +2047 +2047 +2046 +2 +1 0 -1 -2 -2047 -2048 -2048 VINP - VINN VREFP = 2.162V VREFN = 1.138V
BINARY D11D0
BINARY D11D0
(
)
1000 0000 0000 1000 0000 0000 1000 0000 0001 1100 0000 0011 1100 0000 0001 1100 0000 0000 0100 0000 0000 0100 0000 0001 0000 0000 0001 0000 0000 0000 0000 0000 0000
0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
>+1.0235V (DATA OUT OF RANGE) +1.0235V +1.0230V +0.0010V +0.0005V +0.0000V -0.0005V -0.0010V -1.0235V -1.0240V <-1.0240V (DATA OUT OF RANGE)
18
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
1 LSB =
2 x VREF 4096 VREF
VREF = VREFP - VREFN VREF 0x800 0x801 0x803
1 LSB =
2 x VREF 4096 VREF
VREF = VREFP - VREFN VREF
TWO'S COMPLEMENT OUTPUT CODE (LSB)
0x7FF 0x7FE 0x7FD
0x001 0x000 0xFFF
GRAY OUTPUT CODE (LSB)
-2047 -2045 -1 0 +1 +2045 +2047
0xC01 0xC00 0x400
0x803 0x802 0x801 0x800 DIFFERENTIAL INPUT VOLTAGE (LSB)
0x002 0x003 0x001 0x000
-2047 -2045 -1 0 +1 +2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Two's Complement Transfer Function (G/T = 0)
Figure 8. Gray Code Transfer Function (G/T = 1)
MAX1208 is in normal operating mode. With PD high, the MAX1208 is in power-down mode. The power-down mode allows the MAX1208 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX1208 parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to 1A, and the digital supply current reduces to 0.9A. The following list shows the state of the analog inputs and digital outputs in power-down mode: * INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). * REFOUT has approximately 17k to GND. * REFP, COM, and REFN go high impedance with respect to VDD and GND, but there is an internal 4k resistor between REFP and COM, as well as an internal 4k resistor between REFN and COM. * D11-D0, DOR, and DAV go high impedance. * CLKP and CLKN go high impedance (Figure 5).
The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 10ms with the recommended capacitor array (Figure 13). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers.
Applications Information
Using Transformer Coupling
In general, the MAX1208 provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 10) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1208 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a
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19
12-Bit, 80Msps, 3.3V ADC MAX1208
BINARY-TO-GRAY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D11 0 0 1 1 1 D7 0 1 0 0 D3 1 1 0 D0 0 BIT POSITION BINARY GRAY CODE
GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 0 1 0 0 D7 1 1 1 0 D3 1 0 1 D0 0 BIT POSITION GRAY CODE BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: GRAY10 = BINARY10 + BINARY11 GRAY10 = 1 + 0 GRAY10 = 1
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: BINARY10 = BINARY11 + GRAY10 BINARY10 = 0 + 1 BINARY10 = 1
D11 0 0 + 1 1 1 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0
D11 1 + 0 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
3) REPEAT STEP 2 UNTIL COMPLETE: GRAY9 = BINARY9 + BINARY10 GRAY9 = 1 + 1 GRAY9 = 0
3) REPEAT STEP 2 UNTIL COMPLETE: BINARY9 = BINARY10 + GRAY9 BINARY9 = 1 + 0 BINARY9 = 1
D11 0 0 1 1 + 1 0 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0 0
D11 1 + 1 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
4) THE FINAL GRAY CODE CONVERSION IS: D11 0 0 1 1 1 0 1 0 D7 0 1 1 1 0 1 0 0 D3 1 1 1 0 0 1 D0 0 0 BIT POSITION BINARY GRAY CODE
4) THE FINAL BINARY CONVERSION IS: D11 0 0 1 1 0 1 0 1 D7 1 0 1 1 1 0 0 0 D3 1 1 0 1 1 0 D0 0 0 BIT POSITION GRAY CODE BINARY
EXCLUSIVE OR TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y = A + 0 1 1 0 B
Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion
20
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
24.9 0.1F VIN N.C. 1 T1 2 5 2.2F 3 4 MINICIRCUITS TT1-6 OR T1-1T 24.9 INN 12pF COM 6 12pF INP VIN
MAX4108 0.1F INP 5.6pF 100 24.9 COM 2.2F 100 24.9 INN 5.6pF
MAX1208
MAX1208
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist
Figure 12. Single-Ended, AC-Coupled Input Drive
step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 10 is good for frequencies up to Nyquist (fCLK / 2). The circuit of Figure 11 converts a single-ended input signal to fully differential just as Figure 10. However, Figure 11 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 75 termination to the signal source. The second set of termina-
tion resistors connects to COM, providing the correct input common-mode voltage. Two 0 resistors in series with the analog inputs allow high IF input frequencies. These 0 resistors can be replaced with low-value resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 12 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.
0* 0.1F VIN N.C. 1 T1 2 5 75 0.5% 6 75 0.5% N.C. 1 T2 2 5 N.C. 110 0.1% 2.2F 0* INN 5.6pF *0 RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. 6 110 0.1% 5.6pF INP
MAX1208
COM
3 4 MINICIRCUITS ADT1-1WT
3 4 MINICIRCUITS ADT1-1WT
Figure 11. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
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21
12-Bit, 80Msps, 3.3V ADC MAX1208
+3.3V 2.2F 0.1F +3.3V 1 2 0.1F
MAX6029EUK21
0.1F 5 2.048V NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 15mA AND SINKING 30mA OF OUTPUT CURRENT. 0.1F 16.2k 1 1F 3 2 5 +3.3V 0.1F
VDD 38 REFOUT
REFP
1
1F*
10F
MAX1208
REFN 2
0.1F 3 REFIN GND COM 2.2F
39
MAX4230
4 47
2.048V
+3.3V 10F 6V 330F 6V 2.2F 0.1F 0.1F
1.47k VDD *PLACE THE 1F REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. 0.1F 38 REFOUT 1F* 10F REFP 1
MAX1208
REFN 2
0.1F 3 REFIN GND COM 2.2F
39
Figure 13. External Buffered Reference Driving Multiple ADCs
Buffered External Reference Drives Multiple ADCs
The buffered external reference mode allows for more control over the MAX1208 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50M.
Figure 13 uses the MAX6029EUK21 precision 2.048V reference as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a one-pole, 10Hz lowpass filter to the MAX4230. The MAX4230 buffers the 2.048V reference and provides additional 10Hz lowpass filtering before its output is applied to the REFIN input of the MAX1208.
22
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
+3.3V 1 0.1F 2
MAX6029EUK30
+3.3V 5 3.000V 0.1F 1 24.3k 1% 20k 1% 3 2 5 0.1F +3.3V 0.1F 2.2F
MAX4230
4 47
2.157V 1 330F 6V REFP VDD REFOUT 38 0.1F
10F 6V
10F
1F*
MAX1208
1.47k 2 0.1F REFN +3.3V
0.47F 26.7k 1%
0.1F
1 26.7k 1% 3
5
MAX4230
4 47
3 1.649V 2.2F
COM
GND
REFIN
39
2
10F 6V
330F 6V 0.1F
+3.3V 2.2F 0.1F
20k 1% 20k 1% 20k 1% 0.1F +3.3V
1.47k 1 1 3 2 VDD REFOUT 1.141V 47 10F 1F* 38 0.1F
REFP
5
MAX4230
4
MAX1208
2 330F 6V REFN
10F 6V
0.1F
1.47k *PLACE THE 1F REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. 2.2F
3
COM
GND
REFIN
39
Figure 14. External Unbuffered Reference Driving Multiple ADCs
Unbuffered External Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX1208 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, and allows REFP, REFN, and COM to be driven directly by a set of external reference sources.
Figure 14 uses the MAX6029EUK30 precision 3.000V reference as a common reference for multiple converters. A five-component resistive divider chain follows the MAX6029 voltage reference. The 0.47F capacitor along this chain creates a 10Hz lowpass filter. Three MAX4230 operational amplifiers buffer taps along this resistor chain providing 2.157V, 1.649V, and 1.141V to the MAX1208's REFP, COM, and REFN reference inputs,
23
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC MAX1208
respectively. The feedback around the MAX4230 op amps provides additional 10Hz lowpass filtering. The 2.157V and 1.141V reference voltages set the full-scale analog input range to 1.016V. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX1208, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Grounding, Bypassing, and Board Layout
The MAX1208 requires high-speed board layout design techniques. Refer to the MAX1211 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX1208 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX1208 relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1211 evaluation kit data sheet for an example of symmetric input layout.
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale MAX1208 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX1208 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to www.maxim-ic.com for application notes on thermal + quantization noise floor.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX1208, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76
24
______________________________________________________________________________________
12-Bit, 80Msps, 3.3V ADC
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset.
MAX1208
2 2 2 2 VIM1 + VIM 2 + ....... + VIM13 + VIM14 IMD = 20 x log 2 2 V1 + V2

Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. Fourteen intermodulation products (VIM_) are used in the MAX1208 IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where fIN1 and fIN2 are the fundamental input tone frequencies: * Second-order intermodulation products: fIN1 + fIN2, fIN2 - fIN1 * Third-order intermodulation products: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 * Fourth-order intermodulation products: 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1 * Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1
Single-Tone Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset.
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:
2 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 + V7 THD = 20 x log V1
Two-Tone Spurious-Free Dynamic Range (SFDRTT)
SFDRTT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic.
where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2-HD7).
Aperture Delay
The MAX1208 samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4).
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as:
Aperture Jitter
Figure 4 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
______________________________________________________________________________________
25
12-Bit, 80Msps, 3.3V ADC MAX1208
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to the thermal + quantization noise parameter and is an indication of the ADC's overall noise performance. No fundamental input tone is used to test for nOUT; INP, INN, and COM are connected together and 1024k data points collected. nOUT is computed by taking the RMS value of the collected data points.
REFOUT
Pin Configuration
OVDD GND DAV VDD G/T I.C. I.C. 30 29 28 27 26 25 24 23 22 EXPOSED PADDLE (GND) 11 12 13 14 15 16 17 18 19 20 CLKTYP D11 GND OVDD DOR D10 VDD VDD VDD VDD 21 TOP VIEW REFIN
40 39 38 37 36 35 34 33 32 31 REFP REFN COM GND INP INN GND DCE CLKN CLKP 1 2 3 4 5 6 7 8 9 10 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Overdrive Recovery Time
Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX1208 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by 10%.
THIN QFN 6mm x 6mm x 0.8mm
26
______________________________________________________________________________________
PD
MAX1208
12-Bit, 80Msps, 3.3V ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
MAX1208
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k
e (ND-1) X e
L
e L
C L C L
L1 L L
e
e
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1
2
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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